PXS20RM Datasheet, PDF (1189/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Register Protection (REG_PROT)
40.4.2.1 Change lock settings directly via area #4
Memory area #4 contains the lock bits. They can be modified by writing to them. Each SLBRn[SLBm] bit
has a mask bit SLBRn[WEm] which protects it from being modified. This masking makes
clear-modify-write operations unnecessary.
Figure 40-6 shows two modification examples. In the left example there is a write access to the SLBRn
register specifying a mask value which allows modification of all SLBRn[SLBm] bits. The example on the
right specifies a mask which only allows modification of the bits SLBRn[SLB{3:1}].
to SLB0 to SLB1 to SLB2 to SLB3 write data
to SLB0 to SLB1 to SLB2 to SLB3 write data
1
1
1
1 SLBRn[WE{3:0}]
0
1
1
1 SLBRn[WE{3:0}]
change allowed
change allowed
SLB0 SLB1 SLB2 SLB3 SLBRn[SLB{3:0}]
SLB0 SLB1 SLB2 SLB3 SLBRn[SLB{3:0}]
Figure 40-6. Change lock settings directly via area #4
Figure 40-6 showed four registers that can be protected with 8-bit protection. Registers with 16- and 32-
bit protection are shown in Figure 40-7 and Figure 40-8, respectively.
to SLB0 to SLB1 to SLB2 to SLB3 write data
to SLB0 to SLB1 to SLB2 to SLB3 write data
1
X
1
X SLBRn[WE{3:0}]
1
X
0
0 SLBRn[WE{3:0}]
update lock bits
SLB0 SLB1 SLB2 SLB3 SLBR
update lock bits
SLB0 SLB1 SLB2 SLB3 SLBR
Figure 40-7. Change lock settings for 16-bit protected addresses
On the right side of Figure 40-7 you can see that the data written to SLBRn[SLB{0}] is automatically
written to SLBRn[SLB{1}] as well. This is done because the address reflected by SLBRn[SLB{0}] is has
16-bit protection. Note that in this case the write enable SLBRn[WE{0}] must be set while
SLBRn[WE{1}] does not matter. As the enable bits SLBRn[WE{3:2}] are cleared the lock bits
SLBRn[SLB{3:2}] remain unchanged.
In the example on the left side of Figure 40-7 the data written to SLBRn[SLB{0}] is mirrored to
SLBRn[SLB{1}] and the data written to SLBRn[SLB{2}] is mirrored to SLBRn[SLB{3}] as for both
registers the write enables are set.
Figure 40-8 shows a register with 32-bit protection. When SLBRn[WE{0}] is set the data written to
SLBRn[SLB{0}] is automatically written to SLBRn[SLB{3:1}] also. Otherwise SLBRn[SLB{3:0}]
remains unchanged.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
40-7