PXS20RM Datasheet, PDF (636/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexCAN Module
to the MB. If the MB is not unlocked in time and yet another new message with the same ID arrives, then
the new message overwrites the one on the SMB and there will be no indication of lost messages either in
the Code field of the MB or in the Error and Status Register.
While the message is being moved-in from the SMB to the MB, the BUSY bit on the Code field is asserted.
If the CPU reads the Control and Status word and finds out that the BUSY bit is set, it should defer
accessing the MB until the BUSY bit is negated.
NOTE
If the BUSY bit is asserted or if the MB is empty, then reading the Control
and Status word does not lock the MB.
Deactivation takes precedence over locking. If the CPU deactivates a locked Rx MB, then its lock status
is negated and the MB is marked as invalid for the current matching round. Any pending message on the
SMB will not be transferred anymore to the MB.
24.4.7 Rx FIFO
The receive-only FIFO is enabled by asserting the FEN bit in the MCR. The reset value of this bit is zero
to maintain software backwards compatibility with previous versions of the module that did not have the
FIFO feature. When the FIFO is enabled, the memory region normally occupied by the first 8 MBs
(0x80-0xFF) is now reserved for use of the FIFO engine (see Section 24.3.3, Rx FIFO Structure).
Management of read and write pointers is done internally by the FIFO engine. The CPU can read the
received frames sequentially, in the order they were received, by repeatedly accessing a Message Buffer
structure at the beginning of the memory.
The FIFO can store up to six frames pending service by the CPU. An interrupt is sent to the CPU when
new frames are available in the FIFO. Upon receiving the interrupt, the CPU must read the frame
(accessing an MB in the 0x80 address) and then clear the interrupt. The act of clearing the interrupt triggers
the FIFO engine to replace the MB in 0x80 with the next frame in the queue, and then issue another
interrupt to the CPU. If the FIFO is full and more frames continue to be received, an OVERFLOW
interrupt is issued to the CPU and subsequent frames are not accepted until the CPU creates space in the
FIFO by reading one or more frames. A warning interrupt is also generated when five frames are
accumulated in the FIFO.
A powerful filtering scheme is provided to accept only frames intended for the target application, thus
reducing the interrupt servicing work load. The filtering criteria is specified by programming a table of
eight 32-bit registers that can be configured to one of the following formats (see also Section 24.3.3, Rx
FIFO Structure):
• Format A: 8 extended or standard IDs (including IDE and RTR)
• Format B: 16 standard IDs or 16 extended 14-bit ID slices (including IDE and RTR)
• Format C: 32 standard or extended 8-bit ID slices
NOTE
A chosen format is applied to all 8 registers of the filter table. It is not
possible to mix formats within the table.
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PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor