PXS20RM Datasheet, PDF (365/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
return the correct values when read, but writing to them has no effect. Writing to the DSPI_TCR during
module disable mode has no effect. Interrupt and DMA request signals cannot be cleared while in the
module disable mode.
16.5 Initialization/Application Information
16.5.1 How to Manage DSPI Queues
The queues are not part of the DSPI, but the DSPI includes features in support of queue management.
Queues are primarily supported in SPI Configuration.
1. When DSPI executes last command word from a queue, the EOQ bit in the command word is set
to indicate to the DSPI that this is the last entry in the queue.
2. At the end of the transfer, corresponding to the command word with EOQ set is sampled, the EOQ
flag (EOQF) in the DSPI_SR is set.
3. The setting of the EOQF flag disables serial transmission and reception of data, putting the DSPI
in the STOPPED state. The TXRXS bit is cleared to indicate the STOPPED state.
4. The DMA can continue to fill TX FIFO until it is full or step 5 occurs.
5. Disable DSPI DMA transfers by disabling the DMA enable request for the DMA channel assigned
to TX FIFO and RX FIFO. This is done by clearing the corresponding DMA enable request bits in
the DMA Controller.
6. Ensure all received data in RX FIFO has been transferred to memory receive queue by reading the
RXCNT in DSPI_SR or by checking RFDF in the DSPI_SR after each read operation of the
DSPI_POPR.
7. Modify DMA descriptor of TX and RX channels for new queues
8. Flush TX FIFO by writing a ‘1’ to the CLR_TXF bit in the DSPI_MCR. Flush RX FIFO by writing
a ‘1’ to the CLR_RXF bit in the DSPI_MCR.
9. Clear transfer count either by setting CTCNT bit in the command word of the first entry in the new
queue or via CPU writing directly to SPI_TCNT field in the DSPI_TCR.
10. Enable DMA channel by enabling the DMA enable request for the DMA channel assigned to the
DSPI TX FIFO, and RX FIFO by setting the corresponding DMA set enable request bit.
11. Enable serial transmission and serial reception of data by clearing the EOQF bit.
16.5.2 Switching Master and Slave Mode
When changing modes in the DSPI, follow the steps below to guarantee proper operation.
1. Halt the DSPI by setting DSPI_MCR[HALT].
2. Clear the transmit and receive FIFOs by writing a 1 to the CLR_TXF and CLR_RXF bits in
DSPI_MCR.
3. Set the appropriate mode in DSPI_MCR[MSTR] and enable the DSPI by clearing
DSPI_MCR[HALT].
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
16-45