PXS20RM Datasheet, PDF (692/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flexible Motor Control Pulse Width Modulator Module (FlexPWM)
PWMBFS - PWMB Fault State
These bits determine the fault state for the PWMB output during fault conditions and STOP mode. It
may also define the output state during WAIT and DEBUG modes depending on the settings of
WAITEN and DBGEN.
• 00 = Output is forced to logic 0 state prior to consideration of output polarity control.
• 01 = Output is forced to logic 1 state prior to consideration of output polarity control.
• 1x = Output is tristated.
PWMXFS - PWMX Fault State
These bits determine the fault state for the PWMX output during fault conditions and STOP mode. It
may also define the output state during WAIT and DEBUG modes depending on the settings of
WAITEN and DBGEN.
• 00 = Output is forced to logic 0 state prior to consideration of output polarity control.
• 01 = Output is forced to logic 1 state prior to consideration of output polarity control.
• 1x = Output is tristated.
25.4.3.12 Status Register (STS)
PWM_SUB
_BASE+$1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A
Read
Write
0 RUF
0
REF RF
0
0
0 _{CFX CFX}
10
CMPF
Reset
0000000000000000
Figure 25-46. Status Register (STS)
RUF - Registers Updated Flag
This read only flag is set when one of the INIT, VALx, FRACx, or PRSC registers has been written
resulting in non-coherent data in the set of double buffered registers. Clear RUF by a proper reload
sequence consisting of a reload signal while LDOK = 1. Reset clears RUF.
1 = At least one of the double buffered registers has been updated since the last reload.
0 = No register update has occurred since last reload.
REF - Reload Error Flag
This read/write flag is set when a reload cycle occurs while LDOK is 0 and the double buffered
registers are in a non-coherent state (RUF = 1). Clear REF by writing a logic one to the REF bit. Reset
clears REF.
1 = Reload signal occurred with non-coherent data and LDOK = 0.
0 = No reload error occurred.
RF - Reload Flag
This read/write flag is set at the beginning of every reload cycle regardless of the state of the LDOK
bit. Clear RF by writing a logic one to the RF bit when VALDE is clear (non-DMA mode). RF can also
be cleared by the DMA done signal when VALDE is set (DMA mode). Reset clears RF.
25-46
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor