PXS20RM Datasheet, PDF (162/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Analog-to-Digital Converter (ADC)
Table 9-2. ADC memory map (continued)
Address offset
Register
0x2E0
0x2E4–0x2EC
0x2F0
0x2F4–0x33C
0x340
0x344
0x348
0x34C
0x350
0x354
0x358
0x35C
0x360–0x36C
0x370
0x374
0x378–0x37C
0x380
0x384
0x388
0x38C
0x390
0x394
0x398
Channel Watchdog Enable Register 0 (CWENR0)
Reserved
Analog Watchdog Out of Range Register 0 (AWORR0)
Reserved
Self Test Configuration Register 1 (STCR1)
Self Test Configuration Register 2 (STCR2)
Self Test Configuration Register 3 (STCR3)
Self Test Baud Rate Register (STBRR)
Self Test Status Register 1 (STSR1)
Self Test Status Register 2 (STSR2)
Self Test Status Register 3 (STSR3)
Self Test Status Register 4 (STSR4)
Reserved
Self Test Data Register 1 (STDR1)
Self Test Data Register 2 (STDR2)
Reserved
Self Test Analog Watchdog Register 0 (STAW0R)
Self Test Analog Watchdog Register 1A (STAW1AR)
Self Test Analog Watchdog Register 1B (STAW1BR)
Self Test Analog Watchdog Register 2 (STAW2R)
Self Test Analog Watchdog Register 3 (STAW3R)
Self Test Analog Watchdog Register 4 (STAW4R)
Self Test Analog Watchdog Register 5 (STAW5R)
Location
on page 9-21
on page 9-21
on page 9-22
on page 9-23
on page 9-25
on page 9-26
on page 9-27
on page 9-29
on page 9-29
on page 9-30
on page 9-30
on page 9-31
on page 9-31
on page 9-32
on page 9-33
on page 9-33
on page 9-34
on page 9-34
9.3.2 Control logic registers
9.3.2.1 Main Configuration Register (MCR)
The Main Configuration Register (MCR) provides configuration settings for the ADC.
PXS20 Microcontroller Reference Manual, Rev. 1
9-4
Freescale Semiconductor