PXS20RM Datasheet, PDF (1040/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

LIN Controller (LINFlexD)
The TCD settings (word transfer) are shown in Table 31-47. All other TCD fields = 0. TCD settings based
on half-word or byte transfer are allowed.
Table 31-47. TCD settings (slave node, RX mode)
TCD Field
Value
Description
CITER[14:0]
BITER[14:0]
NBYTES[31:0]
1
1
[4] + 4/8 = N
SADDR[31:0]
BDRL address
SOFF[15:0]
4
SSIZE[2:0]
2
SLAST[31:0]
–N
DADDR[31:0]
RAM address
DOFF[15:0]
4
DSIZE[2:0]
2
DLAST_SGA[31:0] –N
INT_MAJ
0/1
D_REQ
1
START
0
Single iteration for the “major” loop
Single iteration for the “major” loop
Data buffer is stuffed with dummy bytes if the length
is not word aligned.
BIDR + BDRL + BDRM
Word increment
Word transfer
Word increment
Word transfer
No scatter/gather processing
Interrupt disabled/enabled
Only on the last TCD of the chain.
No software request
31.11.5 UART node, TX mode
In UART TX mode, the DMA interface requires a DMA TX channel. A single TCD can control the
transmission of an entire Tx buffer. The memory map associated with the TCD chain (RAM area and
LINFlexD registers) is shown in Figure 31-51.
RAM area
LINFlex2 registers
DMA transfer (8/16-bits data format)
TCD (n)
BDRL
(M bytes)
BDRL
(M half-words)
BDRL
(4 bytes FIFO mode)
BDRL
(2 half-words FIFO mode)
Buffer (n)
TCD (n+1)
BDRL
(M bytes)
BDRL
(M half-words)
BDRL
(4 bytes FIFO mode)
BDRL
(2 half-words FIFO mode)
Buffer (n+1)
1 DMA TX channel (TCD single and/or linked chain)
Figure 31-51. TCD chain memory map (UART node, TX mode)
31-64
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor