PXS20RM Datasheet, PDF (349/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
The TXNXTPTR field indicates which TX FIFO Entry will be transmitted during the next transfer. The
TXNXTPTR contains the positive offset from DSPI_TXFR0 in number of 32-bit registers. For example,
TXNXTPTR equal to two means that the DSPI_TXFR2 contains the SPI data and command for the next
transfer. The TXNXTPTR field is incremented every time SPI data is transferred from the TX FIFO to the
shift register. The maximum value of the field is equal to DSPI_HCR[TXFR] and it rolls over after
reaching the maximum.
Because the PUSHR is a 32-bit register, any writes to PUSHR will transfer the all 32 bits of data from the
write data bus to the register. Data byte strobes are ignored.
16.4.2.4.1 Filling the TX FIFO
Host software or other intelligent blocks can add (push) entries to the TX FIFO by writing to the
DSPI_PUSHR. When the TX FIFO is not full, the TX FIFO Fill Flag (TFFF) in the DSPI_SR is set. The
TFFF bit is cleared when TX FIFO is full and the DMA controller indicates that a write to DSPI_PUSHR
is complete. Writing a ‘1’ to the TFFF bit also clears it. The TFFF can generate a DMA request or an
interrupt request. See Section 16.4.6.2, Transmit FIFO Fill Interrupt or DMA Request, for details.
The DSPI ignores attempts to push data to a full TX FIFO, the state of the TX FIFO does not change and
no error condition is indicated.
16.4.2.4.2 Draining the TX FIFO
The TX FIFO entries are removed (drained) by shifting SPI data out through the shift register. Entries are
transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the
TX FIFO. Every time an entry is transferred from the TX FIFO to the shift register, the TX FIFO Counter
decrements by one. At the end of a transfer, the TCF bit in the DSPI_SR is set to indicate the completion
of a transfer. The TX FIFO is flushed by writing a ‘1’ to the CLR_TXF bit in DSPI_MCR.
If an external bus master initiates a transfer with a DSPI slave while the slave’s DSPI TX FIFO is empty,
the Transmit FIFO Underflow Flag (TFUF) in the slave’s DSPI_SR is set. See Section 16.4.6.4, Transmit
FIFO Underflow Interrupt Request, for details.
The TFFF and TCF bits in the DSPI_SR are independent of each other. The TX FIFO is updated (and the
TFFF field is updated) whenever the TX data is loaded into the shift register. The TCF bit is updated when
all of the TX data is shifted out.
16.4.2.5 Receive First In First Out (RX FIFO) Buffering Mechanism
The RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds from one to
sixteen received SPI data frames. The number of entries in the RX FIFO is SoC specific. SPI data is added
to the RX FIFO at the completion of a transfer when the received data in the shift register is transferred
into the RX FIFO. SPI data are removed (popped) from the RX FIFO by reading the DSPI POP RX FIFO
Register (DSPI_POPR). RX FIFO entries can only be removed from the RX FIFO by reading the
DSPI_POPR or by flushing the RX FIFO.
The RX FIFO Counter field (RXCTR) in the DSPI Status Register (DSPI_SR) indicates the number of
valid entries in the RX FIFO. The RXCTR is updated every time the DSPI _POPR is read or SPI data is
copied from the shift register to the RX FIFO.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
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