PXS20RM Datasheet, PDF (897/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Frequency-Modulated Phase-Locked Loop (FMPLL)
Chapter 27
Frequency-Modulated Phase-Locked Loop (FMPLL)
27.1 Introduction
This section describes the features and functions of the two independent FMPLL modules implemented in
PXS20.
27.2 Overview
The FMPLLs allow the user to generate high speed system clocks from a common 4–40 MHz input clock.
Further, the FMPLLs support programmable frequency modulation of the system clock. The FMPLL
multiplication factor and the output clock divider ratio are software-configurable.
PXS20 has two FMPLLs: one for the system clock using frequency modulation (FM) and one that can be
used for motor control peripherals.
The FMPLL’s block diagram is shown in Figure 27-1.
CLKIN
Phase/frequency detector
IDF
Charge pump
Loop filter
VCO
PHI
ODF
NDIV
Loop
Frequency
Divider
Figure 27-1. FMPLL block diagram
27.3 Features
The FMPLL has the following major features:
• Input clock frequency from 4–40 MHz
• Voltage controlled oscillator (VCO) range from 256–512 MHz (see Section 27.7, Requirements)
• Reduced frequency divider (RFD) for reduced frequency operation without forcing the FMPLL to
relock
• Frequency modulated phase-locked loop (FMPLL)
— Modulation enabled/disabled through software
— Triangle wave modulation
• Programmable modulation depth
— ±0.25% to ±4% deviation from center spread frequency
— –0.5% to –8% deviation from down spread frequency
— Programmable modulation frequency dependent on reference frequency
• Self-clocked mode (SCM) operation
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
27-1