PXS20RM Datasheet, PDF (229/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Clock Generation Module (MC_CGM)
Table 11-12. Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) field descriptions
Field
Description
DE0
DIV0
Divider 0 Enable
0 Disable auxiliary clock 2 divider 0
1 Enable auxiliary clock 2 divider 0
Divider 0 Division Value — The resultant FlexCAN clock will have a period DIV0 + 1 times that of auxiliary
clock 2. If the DE0 is set to 0 (Divider 0 is disabled), any write access to the DIV0 field is ignored and the
FlexCAN clock remains disabled.
11.3.1.11 Auxiliary Clock 3 Select Control Register (CGM_AC3_SC)
Address 0xC3FE_0390
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
W
SELCTL
0
0
0
0
0
0
0
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 11-13. Auxiliary Clock 3 Select Control Register (CGM_AC3_SC)
This register is used to select the current clock source for the following clocks:
• undivided: PLL0 reference clock
Table 11-13. Auxiliary Clock 3 Select Control Register (CGM_AC3_SC) Field Descriptions
Field
Description
SELCT Auxiliary Clock 3 Source Selection Control — This value selects the current source for auxiliary clock
L 3.
0000 16 MHz int. RC osc.
0001 4-40 MHz crystal osc.
0010 reserved
0011 reserved
0100 reserved
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
11-15