PXS20RM Datasheet, PDF (1013/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

31.10.7 LIN timeout control status register (LINTCSR)
LIN Controller (LINFlexD)
Offset: 0x18
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
00000
IOT¹
CNT
W
w1c w1c w1c
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
1 _{These fields are writable only in Initialization mode (LINCR1[INIT] = 1).}
Figure 31-24. LIN timeout control status register (LINTCSR)
Table 31-19. LINTCSR field descriptions
Name
LTOM
IOT
TOCE
CNT
Description
LIN timeout mode
0: LIN timeout mode (header, response and frame timeout detection)
1: Output compare mode
This bit can be set/cleared in Initialization mode only.
Idle on Timeout
0: LIN state machine not reset to Idle on timeout event
1: LIN state machine reset to Idle on timeout event
This bit can be set/cleared in Initialization mode only.
Timeout counter enable
0: Timeout counter disable. OCF bit in LINESR or UARTSR is not set on an output compare event.
1: Timeout counter enable. OCF bit is set if an output compare event occurs.
TOCE bit is configurable by software in Initialization mode. If LIN state is not Init and if timer is in LIN
timeout mode, then hardware takes control of TOCE bit.
Counter Value
These bits indicate the LIN Timeout counter value.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
31-37