PXS20RM Datasheet, PDF (674/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flexible Motor Control Pulse Width Modulator Module (FlexPWM)
Pin Input
INP_SEL
0
reset
1
8 bit
counter ^EDGCNT
CIE0
Circuit 0
CF0
Int
Capture
EDG0
EDGCNT_EN
Arming
Logic
EDGCMP
This logic is repeated for
PWMA, PWMB, and PWMX
inputs.
Submodule
Timer
EDGx bits
00 - Disabled
01 - Capture falling edges
10 - Capture rising edges
11 - Capture any edge
EDG1
Capture
CF1
Circuit 1
Int
CIE1
Figure 25-26. Enhanced Capture (E-Capture) Logic
Based on the mode selection, the mux selects either the pin input or the compare output from the
count/compare circuit to be processed by the capture logic. The selected signal is routed to two separate
capture circuits which work in tandem to capture sequential edges of the signal. The type of edge to be
captured by each circuit is determined by the EDGx1 and EDGx0 bits whose functionality is listed in
Figure 25-26. Also, controlling the operation of the capture circuits is the arming logic which allows
captures to be performed in a free running (continuous) or one shot fashion. In free running mode, the
capture sequences will be performed indefinitely. If both capture circuits are enabled, they will work
together in a ping-pong style where a capture event from one circuit leads to the arming of the other and
vice versa. In one shot mode, only one capture sequence will be performed. If both capture circuits are
enabled, capture circuit 0 is first armed and when a capture event occurs, capture circuit 1 is armed. Once
the second capture occurs, further captures are disabled until another capture sequence is initiated. Both
capture circuits are also capable of generating an interrupt to the CPU.
25.3.3.11 Fault protection
Fault protection can control any combination of PWM output pins. Faults are generated by a logic one on
any of the FAULTx pins. This polarity can be changed via the FLVL bits. Each FAULTx pin can be
mapped arbitrarily to any of the PWM outputs. When fault protection hardware disables PWM outputs,
the PWM generator continues to run, only the output pins are forced to logic 0, logic 1, or tristated
depending the values of the PWMxFS bits.
25-28
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor