PXS20RM Datasheet, PDF (295/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Chapter 15
Crossbar Switch (XBAR)
Crossbar Switch (XBAR)
15.1 Information specific to this device
This section presents device-specific parameterization, customization, and feature availability information
not specifically referenced in the remainder of this chapter.
15.1.1 Register availability
Not all registers listed in Table 15-4 are available on this device. Specifically, this device includes only
registers for:
• Slaves 0, 2, and 7
• Masters 0, 1, 2, 3, 5, and 6
15.1.2 MPR reset value
The reset value of the MPR register on this device is 0x0540_3210.
15.1.3 max_halt signal unavailable
The max_halt signal is unavailable on this device.
15.1.4 Logical master IDs
Table 15-1 defines the logical master ID used for the chip masters in Lock Step Mode (LSM) and
Decoupled Parallel Mode (DPM). The logical master IDs for the two cores are different in DPM so that
they both can access the same XBAR.
Table 15-1. Logical master IDs
Master
Core_0 Instruction port
Core_0 Load/Store port
Core_1 Instruction port
Core_1 Load/Store port
eDMA_0
eDMA_1
Core_0 Nexus
Core_1 Nexus
FlexRay
Logical master ID
LSM
0
DPM
0
1
2
2
6¹
8²
8²
9²
3
3
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
15-1