PXS20RM Datasheet, PDF (494/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
Register address: ECSM Base + 0x0065
0
1
2
3
4
5
6
7
R
PRESR
W
RESET:
-
-
-
-
-
-
-
-
= Unimplemented
Figure 21-17. Platform RAM ECC Syndrome (PRESR) Register
Field
PRESR
Table 21-18. PRESR field descriptions
Description
Platform RAM ECC Syndrome
This 8-bit syndrome field includes 6 bits of Hamming decoded parity plus an odd-parity bit for the
entire 39-bit (32-bit data + 7 ECC) code word. The upper 7 bits of the syndrome specify the exact bit
position in error for single-bit correctable code words, and the combination of a non-zero 7-bit
syndrome plus overall incorrect parity bit signal a multi-bit, non-correctable error.
For correctable single-bit errors, the mapping shown in Table 21-18 associates the upper 7 bits of the
syndrome with the data bit in error.
NOTE
Table 21-18 associates the 8 bits of the syndrome value with the data or ECC
bit in error. This table follows the bit vectoring notation where the LSB=0.
Table 21-19. Platform RAM syndrome mapping for single-bit correctable errors
PRESR
0x01
0x02
0x04
0x07
0x08
0x10
0x20
0x40
0x43
0x45
0x46
0x49
0x4a
0x4c
0x4f
0x51
0x52
0x54
Data Bit in Error
ECC ODD[0]
ECC ODD[1]
ECC ODD[2]
DATA ODD BANK[31]
ECC ODD[3]
ECC ODD[4]
ECC ODD[5]
ECC ODD[6]
DATA ODD BANK[0]
DATA ODD BANK[1]
DATA ODD BANK[2]
DATA ODD BANK[3]
DATA ODD BANK[4]
DATA ODD BANK[5]
DATA ODD BANK[21]
DATA ODD BANK[6]
DATA ODD BANK[7]
DATA ODD BANK[8]
21-20
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor