PXS20RM Datasheet, PDF (720/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.4 Protocol Engine Clocking
The clock for the protocol engine can be generated by two sources. The first source is the internal crystal
oscillator and the second source is an internal FMPLL. The clock source to be used is selected by the clock
source select bit CLKSEL in the Module Configuration Register (FR_MCR).
If the protocol engine is clocked by the internal crystal oscillator, an 40 MHz crystal or CMOS compatible
clock must be connected to the oscillator pins. The crystal or clock must fulfill the requirements given by
the FlexRay Communications System Protocol Specification, Version 2.1 Rev A.
26.5 Memory Map and Register Description
The CC occupies 768 bytes of address space starting atthe base address of the CC is defined by the memory
map of the MCU.
26.5.1 Memory Map
The complete memory map of the CC is shown in Table 26-3. The addresses presented here are the offsets
relative to the CC base address which is defined by the MCU address map.
Table 26-3. FlexRay Memory Map
Offset
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000C
0x000E
0x0010
0x0012
0x0014
0x0016
0x0018
0x001A
0x001C
0x001E
0x0020
0x0022
0x0024
0x0026
Register
Module Configuration and Control
Module Version Register (FR_MVR)
Module Configuration Register (FR_MCR)
System Memory Base Address High Register (FR_SYMBADHR)
System Memory Base Address Low Register (FR_SYMBADLR)
Strobe Signal Control Register (FR_STBSCR)
Reserved
Message Buffer Data Size Register (FR_MBDSR)
Message Buffer Segment Size and Utilization Register (FR_MBSSUTR)
PE Access Registers
PE DRAM Access Register (FR_PEDRAR)
PE DRAM Data Register (FR_PEDRDR)
Interrupt and Error Handling
Protocol Operation Control Register (FR_POCR)
Global Interrupt Flag and Enable Register (FR_GIFER)
Protocol Interrupt Flag Register 0 (FR_PIFR0)
Protocol Interrupt Flag Register 1 (FR_PIFR1)
Protocol Interrupt Enable Register 0 (FR_PIER0)
Protocol Interrupt Enable Register 1 (FR_PIER1)
CHI Error Flag Register (FR_CHIERFR)
Message Buffer Interrupt Vector Register (FR_MBIVEC)
Channel A Status Error Counter Register (FR_CASERCR)
Channel B Status Error Counter Register (FR_CBSERCR)
Access
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
26-8
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor