PXS20RM Datasheet, PDF (190/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Analog-to-Digital Converter (ADC)
Field
AWDE
WDTE
THRH
THRL
Table 9-37. STAW0R field descriptions
Description
Analog watchdog enable
0 The analog watchdog related to the algorithm S (step 0) is disabled
1 The analog watchdog related to the algorithm S (step 0) is enabled
Watchdog timer enable. The watchdog timer verifies:
• Correct sequence of the algorithm (step sequence)
• Execution of the algorithm within the safe time period as defined by STBRR[WDT]
As soon as the watchdog timer is enabled the algorithm starting must be detected within the
safe time period. The watchdog timer is reset each time the algorithm restarts.
Note: This bit should be set only in scan mode.
0 The watchdog timer related to the algorithm S is disabled
1 The watchdog timer related to the algorithm S is enabled
High threshold value for channel n. If the analog watchdog is enabled, the STSR1[ERRn]
status bit is set if STDR1[TCDATA] > THRH.
Low threshold value for channel n. If the analog watchdog is enabled, the STSR1[ERRn]
status bit is set if STDR1[TCDATA] < THRH..
9.3.17.12 Self Test Analog Watchdog Register 1A (STAW1AR)
Address: Base + 0x384
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _AW 0 0 0
W ^DE
THRH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0
W
THRL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Figure 9-36. Self Test Analog Watchdog Register 1A (STAW1AR)
Table 9-38. STAW1AR field descriptions
Field
AWDE
THRH
THRL
Description
Analog watchdog enable
0 The analog watchdog related to the algorithm S (step 1) is disabled
1 The analog watchdog related to the algorithm S (step 1) is enabled
High threshold value (integer part) for test channel for algorithm S (step 1) (unsigned coding)
Low threshold value (integer part) for test channel for algorithm S (step 1) (unsigned coding)
9-32
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor