PXS20RM Datasheet, PDF (525/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Fault Collection and Control Unit (FCCU)
the fault directly in the FAULT root, in order to verify the entire path and reaction. The fault injection
mechanism is optional. The reaction following a fake non-critical fault can be masked. The FCCU_NCFF
is a write-only register with a set of codes corresponding to each non-critical fault injection.
Offset: 0x0DC
Access: User write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0 0
W
FNCFC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-21. FCCU NCF Fake Register (FCCU_NCFF)
Table 22-20. FCCU_NCFF field descriptions
Field
FNCFC
Description
Fake non-critical fault code
00h: Fake non-critical fault injection at non-critical fault source 0
01h: Fake non-critical fault injection at non-critical fault source 1
02h: Fake non-critical fault injection at non-critical fault source 2
..
1Fh: Fake non-critical fault injection at non-critical fault source 31
others: No fault injection
These bits are always read as ‘0’ by software.
22.6.19 FCCU IRQ Status Register (FCCU_IRQ_STAT)
The FCCU_IRQ_STAT register defines the FCCU interrupt status register related to the following events:
• Configuration time-out error
• Alarm interrupt
• NMI interrupt
The external interrupt is asserted if any interrupt status bit of the FCCU_IRQ_STAT is set and the
respective enable bit of the FCCU_IRQ_EN register is also set.
The NMI and ALARM interrupts are asserted and cleared according to the FCCU state. The status bits of
the FCCU_IRQ_STAT trace the status of the related interrupt lines.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
22-25