PXS20RM Datasheet, PDF (924/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Interrupt Controller (INTC)
28.6.2.1 Software vector mode
interrupt_exception_handler:
code to save SRR0 and SRR1
lis
r3,hi(INTC_IACKR_PRC0)
# form INTC_IACKR_PRC0 address
ori
r3,r3,lo(INTC_IACKR_PRC0)
lwz
r3,0x0(r3)
# load INTC_IACKR_PRC0, which clears request to processor
lwz
r3,0x0(r3)
# load address of ISR from vector table
code to enable processor recognition of interrupts and save context required by EABI
mtlr
r3
blrl
# move INTC_IACKR_PRC0 contents into link register
# branch to ISR; link register updated with epilog
# address
epilog:
lis
ori
li
stw
r3,hi(INTC_EOIR_PRC0)
r3,r3,lo(INTC_EOIR_PRC0)
r4,0x0
r4,0x0(r3)
# form INTC_EOIR_PRC0 address
# form 0 to write to INTC_EOIR_PRC0
# store to INTC_EOIR_PRC0, informing INTC to lower priority
code to restore context required by EABI and disable processor recognition of interrupts
code to restore SRR0 and SRR1
rfi
vector_table_base_address:
address of ISR for interrupt with vector 0
address of ISR for interrupt with vector 1
.
.
.
address of ISR for interrupt with vector 510
address of ISR for interrupt with vector 511
ISRx:
code to service the interrupt event
code to clear flag bit which drives interrupt request to INTC
blr
# return to epilog
28.6.2.2 Hardware vector mode
This interrupt exception handler is useful with processor and system bus implementations which support
a hardware vector. This example assumes that each interrupt_exception_handlerx only has space for four
instructions, and therefore a branch to interrupt_exception_handler_continuedx is needed.
interrupt_exception_handlerx:
b
interrupt_exception_handler_continuedx# 4 instructions available, branch to continue
interrupt_exception_handler_continuedx:
code to save SRR0 and SRR1
code to enable processor recognition of interrupts and save context required by EABI
28-18
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor