PXS20RM Datasheet, PDF (173/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Analog-to-Digital Converter (ADC)
9.3.9.2 Presampling Register 0 (PSR0)
Address: Base + 0x084
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{PRE PRE PRE PRE PRE PRE PRE PRE PRE PRE PRE PRE PRE PRE PRE PRE}
W ^{S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0}
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-13. Presampling Register 0 (PSR0)
Table 9-16. PSR0 field descriptions
Field
PRESn
Description
Presampling enable
0 Presampling for channel n is disabled
1 Presampling for channel n is enabled
9.3.10 Conversion timing registers
9.3.10.1 Conversion Timing Register 0 (CTR0)
This register configures the conversion timing for channels 0–14. Timings for channel 15 (the TSENS
channel) are configured using CTR1 (see Section 9.3.10.2, Conversion Timing Register 1 (CTR1)).
Address: Base + 0x094
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
W
OFFSHIFT
INPCMP
INPSAMP
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1
Figure 9-14. Conversion Timing Register 0 (CTR0)
Table 9-17. CTR0 field descriptions
Field
Description
INPLATCH Configuration bit for latching phase duration (see Figure 9-15)
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
9-15