PXS20RM Datasheet, PDF (492/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
Register address: ECSM Base +0x0058
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
PFEDR[63:48]
W
RESET:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PFEDR[47:32]
W
RESET:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
= Unimplemented
Figure 21-14. Platform Flash Memory ECC Data High Register (PFEDRH)
Register address: ECSM Base +0x005C
0
1
2
3
4
5
R
W
RESET:
-
-
-
-
-
-
6
7
8
9
PFEDR[31:16]
10 11 12 13 14 15
-
-
-
-
-
-
-
-
-
-
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PFEDR[15:0]
W
RESET:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
= Unimplemented
Figure 21-15. Platform Flash Memory ECC Data Low Register (PFEDRL)
Table 21-16. PFEDRL and PFEDRH field descriptions
Field
PFEDR
Description
Platform Flash Memory ECC Data
This 64-bit field contains the data associated with the faulting access of the last, properly-enabled
platform flash memory ECC event. The field contains the data value taken directly from the data bus.
21.4.2.16 Platform RAM ECC Address Register (PREAR)
The PREAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in the
platform RAM. Depending on the state of the ECC Configuration Register, an ECC event in the platform
21-18
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor