PXS20RM Datasheet, PDF (943/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

29.2 External signal description
JTAG Controller (JTAGC)
29.2.1 Overview
The JTAGC consists of 5 signals that connect to off chip development tools and allow access to test support
functions. The JTAGC signals are outlined in Table 29-1.
Table 29-1. JTAG Signal Properties
Name
I/O
Function
Reset State
Pull¹
TCK
Input
Test Clock
-
Down
TDI
TDO
Input
Output
Test Data In
Test Data Out
-
Up
High Z²
-
TMS
Input
Test Mode Select
-
Up
JCOMP
Input
JTAG Compliancy
-
Down
NOTES:
1 _{The pull is not implemented in this block. Pullup/pulldown devices are implemented in the pads.}
2 _{TDO output buffer enable is negated when the JTAGC is not in the Shift-IR or Shift-DR states. A}
weak pull may be implemented at the TDO pad for use when JTAGC is inactive.
29.2.2 Detailed Signal Descriptions
This section describes each of the signals listed in Table 29-1 in more detail.
29.2.2.1 TCK - Test Clock Input
Test Clock Input (TCK) is an input pin used to synchronize the test logic and control register access
through the TAP.
29.2.2.2 TDI - Test Data Input
Test Data Input (TDI) is an input pin that receives serial test instructions and data. TDI is sampled on the
rising edge of TCK.
29.2.2.3 TDO - Test Data Output
Test Data Output (TDO) is an output pin that transmits serial output for test instructions and data. TDO is
three-stateable and is actively driven only in the Shift-IR and Shift-DR states of the TAP controller state
machine, which is described in Section 29.4.3, TAP Controller State Machine. The TDO output of this
block is clocked on the falling edge of TCK and sampled by the development tool on the rising edge of
TCK.
29.2.2.4 TMS - Test Mode Select
Test Mode Select (TMS) is an input pin used to sequence the IEEE 1149.1-2001 test control state machine.
TMS is sampled on the rising edge of TCK.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
29-3