PXS20RM Datasheet, PDF (430/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Direct Memory Access (eDMA)
eDMA
addr
wdata[31:0]
eDMA engine
hrdata[63:0]
data_path
SRAM
Transfer
Control
Descriptor (TCD)
pmodel_charb
addr_path
c
o
n
t
r
o
l
0
j
j+1
n-1
rdata[31:0]
Peripheral
Bus
AMBA
Bus
hwdata[63:0]
haddr[31:0]
dma_ipi_int[n-1:0]
dma_ipd_done[n-1:0]
ipd_req[n-1:0]
Figure 19-27. eDMA operation, part 1
In the second part of the basic data flow as shown in Figure 19-28, the modules associated with the data
transfer (addr_path, data_path and control) sequence through the required source reads and destination
writes to perform the actual data movement. The source reads are initiated and the fetched data is
temporarily stored in the data_path module until it is gated onto the AMBA-AHB bus during the
destination write. This source read/destination write processing continues until the inner minor byte count
has been transferred. The dma_ipd_done[n] signal is asserted at the end of the minor byte count transfer.
19-34
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor