PXS20RM Datasheet, PDF (449/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Motor Control Timer (eTimer)
This read only register stores the value captured from the counter. Exactly when a capture occurs is
defined by the CPT1MODE bits. This is actually a 2-deep FIFO and not a single register. This register is
not byte accessible.
20.4.3.4 Capture Register 2 (CAPT2)
eTimer_CHNL_ ₀
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
BASE + $6
Read
CAPT2[15:0]
Write
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 000
Figure 20-6. Capture Register 2 (CAPT2)
This read only register stores the value captured from the counter. Exactly when a capture occurs is
defined by the CPT2MODE bits. This is actually a 2-deep FIFO and not a single register. This register is
not byte accessible.
20.4.3.5 Load Register (LOAD)
eTimer_CHNL ₀
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
_BASE + $8
Read
Write
LOAD[15:0]
Reset
0000 0 0 000 0 0 0 0 000
Figure 20-7. Load Register (LOAD)
This read/write register stores the value used to initialize the counter. This register is not byte accessible.
20.4.3.6 Hold Register (HOLD)
eTimer_CHNL ₀
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
_BASE + $A
Read
HOLD[15:0]
Write
Reset
0000 0 0 0000 0 0 0 000
Figure 20-8. Hold Register (HOLD)
This read only register stores the counter’s value whenever any of the other counters within a module are
read. This is used to support coherent reading of cascaded counters.
20.4.3.7 Counter Register (CNTR)
eTimer_CHNL ₀
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
_BASE + $C
Read
Write
CNTR[15:0]
Reset
0000 0 0 0000 0 0 0 000
Figure 20-9. Counter (CNTR)
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
20-7