PXS20RM Datasheet, PDF (761/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.5.2.36 Sync Frame ID Rejection Filter Register (FR_SFIDRFR)
Base + 0x0046
16-bit write access required
Write: Normal Mode
0
R0
W
Rese
t
0
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00000
SYNFRID
000000000000000
Figure 26-36. Sync Frame ID Rejection Filter Register (FR_SFIDRFR)
This register defines the Sync Frame Rejection Filter ID. The application must update this register outside
of the static segment. If the application updates this register in the static segment, it can appear that the CC
accepts the sync frame in the current cycle.
Table 26-41. FR_SFIDRFR Field Descriptions
Field
SYNFRID
Description
Sync Frame Rejection ID — This field defines the frame ID of a frame that must not be used for
clock synchronization. For details see Section 26.6.15.2, Sync Frame Rejection Filtering.
26.5.2.37 Sync Frame ID Acceptance Filter Value Register (FR_SFIDAFVR)
Base + 0x0048
Write: POC:config
0
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R0 0 0 0 0 0
W
FVAL
Rese
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-37. Sync Frame ID Acceptance Filter Value Register (FR_SFIDAFVR)
This register defines the sync frame acceptance filter value. For details on filtering, see Section 26.6.15,
Sync Frame Filtering.
Table 26-42. FR_SFIDAFVR Field Descriptions
Field
FVAL
Description
Filter Value — This field defines the value for the sync frame acceptance filtering.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-49