PXS20RM Datasheet, PDF (472/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Motor Control Timer (eTimer)
To address this, the compare registers are updated in hardware in the same way the counter register is
re-initialized to the value stored in the LOAD register. The compare load feature allows the user to
calculate new compare values and store them in to the comparator load registers. When a compare event
occurs, the new compare values in the comparator load registers are written to the compare registers
eliminating the use of software to do this.
The compare load feature is intended to be used in variable frequency PWM mode. The COMP1 register
determines the pulse width for the logic low part of OFLAG and COMP2 determines the pulse width for
the logic high part of OFLAG. The period of the waveform is determined by the COMP1 and COMP2
values and the frequency of the primary clock source. See Figure 20-28.
20.5.2.15 MODULO COUNTING Mode
To create a modulo counter using COMP1 and COMP2 as the counter boundaries (instead of $0000 and
$FFFF), set the registers in the following manner. Set CNTMODE to either 100 (quadrature count mode)
or 101 (count with direction mode). Use count through roll-over (LENGTH = 0) and continuous count
(ONCE = 0). Set COMP1 and CMPLD1 to the upper boundary value. Set COMP2 and CMPLD2 to the
lower boundary value. Set CMPMODE = 10 (COMP1 is used when counting up and COMP2 is used when
counting down). Set CLC2 = 110 (load CNTR with value of CMPLD2 on COMP1 compare) and CLC1
= 111 (load CNTR with value of CMPLD1 on COMP2 compare).
20.5.3 Other Features
20.5.3.1 Redundant OFLAG Checking
This mode allows the user to bundle two timer functions generating any pattern to compare their resulting
OFLAG behaviors (output signal).
The redundant mode is used to support online checks for functional safety reasons. Whenever a mismatch
between the two adjacent channels occurs, it is reported via an interrupt to the core and the two outputs are
put into their inactive states. An error is flagged via the RCF flag.
This feature can be tested by forcing a transition on one of the OFLAGs using the VAL and FORCE bits
of the channel.
20.5.3.2 Loopback Checking
This mode is always available in that one channel can generate an OFLAG while another channel uses the
first channels OFLAG as its input to be measured and verified to be as expected.
20.5.3.3 Input Capture Mode
Input capture is used to measure pulse width (by capturing the counter value on two successive input
edges) or waveform period (by capturing the counter value on two consecutive rising edges or two
consecutive falling edges). The Capture Registers store a copy of the counter’s value when an input edge
(positive, negative, or both) is detected. The type of edge to be captured by each circuit is determined by
the CPT1MODE and CPT2MODE bits whose functionality is listed in Table 20-14. Also, controlling the
20-30
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor