|
PXS20RM Datasheet, PDF (45/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller | |||
|
◁ |
Introduction
ADC
â Analog-to-digital converter
BAM
â Boot assist module
CAN
â Controller area network controller
CMU
â Clock monitoring unit
CRC
â Cyclic redundancy check unit
CTU
â Cross Triggering Unit
ECC
â Error correction code
ECSM â Error correction status module
eDMA â Enhanced direct memory access controller
FCCU â Fault collection and control unit
FMPLL â Frequency modulated phase locked loop
INTC
â Interrupt controller
IRCOSC â Internal RC oscillator
JTAG
â Joint Test Action Group interface
MC
â Mode entry, clock, reset, & power
PBRIDGE â Peripheral I/O bridge
PIT
â Periodic interrupt timer
PMU
â Power management unit
PWM
â Pulse width modulator module
RC
â Redundancy checker
RTC
â Real time clock
SEMA4 â Semaphore unit
SIUL
â System integration unit lite
SPI
â Serial peripherals interface controller
SSCM â System status and configuration module
STM
â System timer module
SWG
â Sine wave generator
SWT
â Software watchdog timer
TSENS â Temperature sensor
UART/LIN â Universal asynchronous receiver/transmitter/
local interconnect network
WKPU â Wakeup unit
XOSC â Crystal oscillator
Figure 1-2. PXS20 block diagram (continued)
1.4 Feature details
1.4.1 High-Performance e200z4d Core
The e200z4d Power Architecture® core provides the following features:
⢠2 independent execution units, both supporting fixed-point and floating-point operations
⢠Dual issue 32-bit Power Architecture® technology compliant
â 5-stage pipeline (IF, DEC, EX1, EX2, WB)
â In-order execution and instruction retirement
⢠Full support for Power Architecture® instruction set and Variable Length Encoding (VLE)
â Mix of classic 32-bit and 16-bit instruction allowed
â Optimization of code size possible
⢠Thirty-two 64-bit general purpose registers (GPRs)
⢠Harvard bus (32-bit address, 64-bit data)
â I-Bus interface capable of one outstanding transaction plus one piped with no wait-on-data
return
â D-Bus interface capable of two transactions outstanding to fill AHB pipe
⢠I-cache and I-cache controller
â 4 KB, 256-bit cache line (programmable for 2- or 4-way)
⢠No data cache
⢠16-entry MMU
⢠8-entry branch table buffer
⢠Branch look-ahead instruction buffer to accelerate branching
⢠Dedicated branch address calculator
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
1-5
|
▷ |