PXS20RM Datasheet, PDF (416/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Direct Memory Access (eDMA)
Name
HRSn,
n = 0,... 15
Table 19-24. DMAHRSL field descriptions
Description
DMA Hardware Request Status n
Value
0 A hardware service request for channel n is not
present.
1 A hardware service request for channel n is present.
Note: The hardware request status reflects the state of
the request as seen by the arbitration logic.
Therefore, this status is affected by the
DMAERQn bit.
19.2.1.16 eDMA Channel n Priority (DCHPRIn), n = 0–15
When the fixed-priority channel arbitration mode is enabled (DMACR[ERCA] = 0), the contents of these
registers define the unique priorities associated with each channel. The channel priorities are evaluated by
numeric value, i.e., 0 is the lowest priority, 1 is the next higher priority, then 2, 3, etc. Software must
program the channel priorities with unique values, otherwise a configuration error will be reported. The
range of the priority value is limited to the values of 0–15.
Channel preemption is enabled on a per channel basis by setting the ECP bit in the DCHPRIn register.
Channel preemption allows the executing channel’s data transfers to be temporarily suspended in favor of
starting a higher priority channel. After the preempting channel has completed all of its minor loop data
transfers, the preempted channel is restored and resumes execution. After the restored channel completes
one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting
service, the restored channel will be suspended and the higher priority channel will be serviced. Nested
preemption (attempting to preempt a preempting channel) is not supported. After a preempting channel
begins execution, it cannot be preempted. Preemption is only available when fixed arbitration is selected
for channel arbitration mode.
A channel’s ability to preempt another channel can be disabled by setting the DPA bit in the DCHPRIn
register. When a channel’s preempt ability is disabled, that channel cannot suspend a lower priority
channel’s data transfer; regardless of the lower priority channel’s ECP setting. This allows for a pool of
low priority, large data moving channels to be defined. These low priority channels can be configured to
not preempt each other, thus preventing a low priority channel from consuming the preempt slot normally
available a true, high priority channel. See Figure 19-17 and Table 19-25 for the DCHPRIn definition.
Register address: DMA_Offset + 0x100 + n
0
1
2
3
4
5
6
7
R
ECP
DPA
*
CHPRI[0:3]
W
RESET:
0
0
*
*
*
*
*
*
= Unimplemented,
*
= defaults to channel number (n) after reset
Figure 19-17. eDMA Channel n Priority (DCHPRIn) Register
19-20
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor