PXS20RM Datasheet, PDF (459/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Setting this bit enables interrupts when the TOF bit is set.
TCF2IE - Timer Compare 2 Flag Interrupt Enable
Setting this bit enables interrupts when the TCF2 bit is set.
TCF1IE - Timer Compare 1 Flag Interrupt Enable
Setting this bit enables interrupts when the TCF1 bit is set.
TCFIE - Timer Compare Flag Interrupt Enable
Setting this bit enables interrupts when the TCF bit is set.
Enhanced Motor Control Timer (eTimer)
20.4.3.13 Comparator Load Register 1 (CMPLD1)
eTimer_CHNL ₀
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
_BASE + $18
Read
Write
CMPLD1[15:0]
Reset
0000 0 0 000 0 0 0 0 000
Figure 20-15. Comparator Load 1 (CMPLD1)
This read/write register is the preload value for the COMP1 register. This register can also be used to load
into the CNTR register. This register is not byte accessible. More information on the use of this register
can be found in Section 20.5.2.14, Usage of Compare Load Registers.
20.4.3.14 Comparator Load Register 2 (CMPLD2)
eTimer_CHNL ₀
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
_BASE + $1A
Read
Write
CMPLD2[15:0]
Reset
0000 0 0 0000 0 0 0 000
Figure 20-16. Comparator Load 2 (CMPLD2)
This read/write register is the preload value for the COMP2 register. This register can also be used to load
into the CNTR register. This register is not byte accessible. More information on the use of this register
can be found in Section 20.5.2.14, Usage of Compare Load Registers.
20.4.3.15 Compare and Capture Control Register (CCCTRL)
eTimer_CHNL
_BASE + $1C
Read
Write
Reset
0
1
2
3
4
5
6
7
8
9
10 11 12 13
14
15
CLC2[1:0]
CLC1[1:0]
CMPMODE CPT2
CPT1
ONE
CFWM[1:0]
ARM
[1:0]
MODE[1:0] MODE[1:0]
SHOT
00000000000000 0 0
Figure 20-17. Compare and Capture Control Register (CCCTRL)
CLC2 - Compare Load Control 2
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
20-17