PXS20RM Datasheet, PDF (1342/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

System Status and Configuration Module (SSCM)
Table 48-6. ERROR Field Descriptions
Field
Description
PAE Peripheral Bus Abort Enable. This bit enables bus aborts on any access to a peripheral slot that is not used on the
device. This feature is intended to aid in debugging when developing application code.
1 Illegal accesses to non-existing peripherals produce a Prefetch or Data Abort exception
0 Illegal accesses to non-existing peripherals do not produce a Prefetch or Data Abort exception
RAE
Register Bus Abort Enable. This bit enables bus aborts on illegal accesses to off-platform peripherals. Illegal
accesses are defined as reads or writes to reserved addresses within the address space for a particular peripheral.
This feature is intended to aid in debugging when developing application code.
1 Illegal accesses to peripherals produce a Prefetch or Data Abort exception
0 Illegal accesses to peripherals do not produce a Prefetch or Data Abort exception
Note: Transfers to Peripheral Bus resources may be aborted even before they reach the Peripheral Bus (i.e. at the
AIPS level). In this case, the PER_ABORT and REG_ABORT register bits will have no effect on the abort.
READ
WRITE
Table 48-7. ERROR Allowed Register Accesses
8-bit
16-bit
Allowed
Allowed
Allowed
Allowed
32-bit
Allowed
Not Allowed
48.3.1.4 Debug Status Port Register (DEBUGPORT)
The Debug Status Port register is used to (optionally) provide debug data on a set of pins. Consult the SOC
guide for this information.
Address: Base + 0x0008
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
DEBUG_MODE
W
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Reserved for future use
Figure 48-5. Debug Status Port (DEBUGPORT) Register
48-6
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor