SH7261 Datasheet, PDF (997/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
Bit Bit Name
Initial
Value R/W Description
1
LINK_SDET 0
R
Indicates that a link block was detected within seven
sectors after the start of decoding.
0
LINK_OUT1 0
R
Indicates that the sector after ECC correction has been
identified as a run-out 1 sector.
This bit is only valid when an IERR interrupt is not
generated (i.e. when ECC correction was successful).
21.3.13 ECC/EDC Error Status Register (CROMST6)
CROMST6 indicates ECC processing error or EDC check error before/after ECC correction.
Bit: 7
ST_
ERR
Initial value: 0
R/W: R
6
5
4
3
2
1
0
—
ST_
ST_
ST_
ECCABT ECCNG ECCP
ST_
ECCQ
ST_
EDC1
ST_
EDC2
0
0
0
0
0
0
0
RRRRRRR
Bit Bit Name
Initial
Value R/W Description
7
ST_ERR
0
R
Indicates that the decoded block after ECC correction
contains any error (even in a single byte).
6

0
R
Reserved
This bit is always read as 0 and cannot be modified.
5
ST_ECCABT 0
R
Indicates that ECC processing was discontinued.
This bit is set to 1 when a transition from sector to
sector occurs while ECC correction is in progress. This
does not indicate a problem for ECC correction if the
BUF_NG bit in the CBUFST2 register is 0 at the same
time. Whether or not this is so depends on the timing of
the sector transition.
4
ST_ECCNG 0
R
Indicates that error correction was not possible.
This bit is also set to 1 on detection of a short sector.
3
ST_ECCP
0
R
Indicates that P-parity errors were not corrected in ECC
correction.
This bit is only valid when synchronization is normal
(the sector is neither short nor long).
This bit is set to 1 when the result of syndrome
calculation for P parity is non-0.
Rev. 2.00 Sep. 07, 2007 Page 965 of 1312
REJ09B0320-0200