SH7261 Datasheet, PDF (732/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.9 FIFO Control Register (SCFCR)
SCFCR resets the quantity of data in the transmit and receive data FIFO registers, sets the trigger
data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and
written to by the CPU. It is initialized to H'0000 by a power-on reset or in deep standby mode.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
RTRG[1:0]
TTRG[1:0]
— TFRST RFRST LOOP
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R/W R/W R R/W R/W R/W
Bit
15 to 8
7, 6
Bit Name
—
RTRG[1:0]
Initial
Value
All 0
00
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Receive FIFO Data Trigger
Set the quantity of receive data which sets the receive
data full (RDF) flag in the serial status register (SCFSR).
The RDF flag is set to 1 when the quantity of receive
data stored in the receive FIFO register (SCFRDR) is
increased more than the set trigger number shown
below.
• Asynchronous mode • Clocked synchronous mode
00: 1
00: 1
01: 4
01: 2
10: 8
10: 8
11: 14
11: 14
Note: In clock synchronous mode, to transfer the receive
data using DMAC, set the receive trigger number
to 1. If a number other than 1 is set, CPU must
read the receive data left in SCFRDR.
Rev. 2.00 Sep. 07, 2007 Page 700 of 1312
REJ09B0320-0200