SH7261 Datasheet, PDF (271/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value
R/W Description
2
DPWDST 0
R
Power-Down Transition/Recovery Status
When set to 1, this bit indicates that a transition to or
recovery from power-down mode is in progress for a
channel from SDRAM0 to SDRAM3.
0: Initialization sequence not in progress
1: Initialization sequence in progress
1
DDPDST 0
R
Deep-Power-Down Transition/Recovery Status
When set to 1, this bit indicates that a transition to or
recovery from deep-power-down mode is in progress
for channel SDRAM0 or SDRAM1.
0: Transition/recovery not in progress
1: Transition/recovery in progress
0
DMRSST 0
R
Mode Register Setting Status
When set to 1, this bit indicates that mode register
setting is in progress for channel SDRAM0 or
SDRAM1.
0: Mode register setting not in progress
1: Mode register setting in progress
"Transition to or recovery from in progress" refers to the interval from the point at which the bits
listed in table 9.5 are written to until the corresponding commands are issued.
Table 9.5 List of Status Registers and Bits Requiring Checking
Function
Register
Bits
Self-refresh
SDRFCNT0
DSFENCm, DSFEN
Initialization sequence
SDIR1
DINIRQCm, DINIRQ
Power-down
SDPWDCNT
DPWDCm, DPWD
Deep-power-down
SDDPDCNT
DDPDCm, DDPD
Mode register setting
SDmMOD
DMR
Note:
Execution of a self-refresh, a transition to or recovery from power-down or deep-power-
down mode, an initialization sequence, or mode register setting may only be performed
when all status bits are cleared to 0. Do not rewrite the registers (bits) listed below when
any of the status bits (DSRFST, DINIST, DPWDST, DDPDST, DMRSST) is set to 1.
Rev. 2.00 Sep. 07, 2007 Page 239 of 1312
REJ09B0320-0200