SH7261 Datasheet, PDF (1076/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 I/O Ports
24.1.1 Register Configuration
Table 24.1 lists the port A registers.
Table 24.1 Register Configuration
Register Name
Port A data register H
Port A data register L
Port A port register H
Port A port register L
Abbreviation R/W
PADRH
R/W
PADRL
R/W
PAPRH
R
PAPRL
R
Address
H'FFFE3800
H'FFFE3802
H'FFFE3804
H'FFFE3806
Access Size
8, 16, 32
8, 16
8, 16, 32
8, 16
24.1.2 Port A Data Registers H and L (PADRH and PADRL)
PADRH and PADRL are 16-bit readable/writable registers that store port A data. Bits PA31DR to
PA0DR correspond to pins PA31 to PA0, respectively.
If a pin is set to the general output function, the pin will output the value written to the
corresponding bit in PADRH or PADRL, and the register value is read from PADRH or PADRL
regardless of the state of the pin.
If a pin is set to the general input function, the pin state, not the register value, will be returned if
PADRH or PADRL is read. Also, if a value is written to PADRH or PADRL, although the value
will actually be written, it will have no influence on the state of the pin. Table 24.2 summarizes
the PADRH and PADRL read/write operations.
PADRH and PADRL are initialized to H'0000 by a power-on reset or in deep standby mode.
These registers are not initialized either by a manual reset or by switching to sleep mode or
software standby mode.
Rev. 2.00 Sep. 07, 2007 Page 1044 of 1312
REJ09B0320-0200