SH7261 Datasheet, PDF (1302/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 31 Electrical Characteristics
CKIO
A16 to A2
A12*
SDCSn
T1
T2
(ACT)
T3
(RD)
T4
(RD)
T5
(RD)
T6
(RD)
T7
(PRA)
t_AD2
t_AD2
t_AD2
Row
Address
C0 (Column
Address 0)
C1
t_AD2
t_AD2
t_AD2
C2
t_AD2
C3
t_AD2
t_AD2
t_AD2
t_AD2
t_CSD2
t_CSD2
t_CSD2
PRA
command
t_CSD2
t_RASD t_RASD
t_RASD t_RASD
t_AD2
t_AD2
t_CSD2
t_RASD
SDRAS
SDCAS
SDWE
t_CASD
t_CASD
t_WED2 t_WED2
t_CASD
SDCKE
DQMn
t_DQMD
D31 to D0
(High)
t_RDS2 t_RDH2
t_RDS2 t_RDH2
t_DQMD
Note: * Address pin connected to A10 in SDRAM.
Figure 31.17 Multiple Read Bus Timing for SDRAM Space (Four Data Access, DLC = 2
(Two Cycles), DRCD = 1 (Two Cycles), DPCG = 1 (Two Cycles))
Rev. 2.00 Sep. 07, 2007 Page 1270 of 1312
REJ09B0320-0200