SH7261 Datasheet, PDF (1297/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 31 Electrical Characteristics
Bφ = 60 MHz*²
Item
Symbol Min. Max. Unit Figure
External wait setup time t
WTS
8

ns
Figure 31.14
External wait hold time
t_WTH
5

ns
Figure 31.14
SDRAS delay time
t_RASD
1
13
ns
Figures 31.15 to 31.21
SDCAS delay time
t_CASD
1
13
ns
Figures 31.15 to 31.21
DQM delay time
t
1
DQMD
13
ns
Figures 31.15 to 31.21
CKE delay time
t
1
13
ns
Figure 31.21
CKED
Notes: 1. When writing to the external address space or making SDRAM settings in power-on
reset exception handling or cancellation of deep standby mode, be sure to set bits
ACOSW[3:0] in ACSWR to B'0011 beforehand.
2. The maximum value (f_max) of Bφ (external bus clock) depends on the number of wait
cycles and the system configuration of your board.
CKIO
A27 to A0
BC3 to BC0
CSn
RD
Read
D31 to D0
WR3 to WR0
Write
D31 to D0
Tw1
Tw2
Tw2
Tend (Trd)
Tn1
Ts
t_AD1
t_AD1
t_BCD
t_CSD1
t_RSD
t_CSD1
t_RSD
t_RDS1
t_RDH1
t_BCD
t_WDD1
t_WED1
t_WED1
t_WDH1
Figure 31.10 Basic Bus Timing for External Address Space
(Normal Access, Cycle Wait Control, CS Extended Cycle)
Rev. 2.00 Sep. 07, 2007 Page 1265 of 1312
REJ09B0320-0200