SH7261 Datasheet, PDF (120/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 4 Clock Pulse Generator (CPG)
Initial
Bit
Bit Name Value R/W Description
12
CKOEN
1
R/W Clock Output Enable
Specifies whether a clock is output from the CKIO
pin, or whether the CKIO pin is placed in the level-
fixed state during software standby mode or
cancellation of software standby mode.
If this bit is cleared to 0, the CKIO pin is fixed at low
during software standby mode or cancellation of
software standby mode. Therefore, the malfunction of
an external circuit because of an unstable CKIO
clock during cancellation of software standby mode
can be prevented. In clock operating mode 3, the
CKIO pin functions as an input regardless of this bit
value.
0: The CKIO pin is fixed to the low level during
software standby mode or cancellation of software
standby mode.
1: Clock is output from CKIO pin (low level in
software standby mode).
11

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8 STC[2:0] 000
R/W Frequency Multiplication Ratio of PLL Circuit 1
000: × 1 time
001: × 2 times
010: × 3 times
011: × 4 times
100: × 6 times
101: × 8 times
7

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Sep. 07, 2007 Page 88 of 1312
REJ09B0320-0200