SH7261 Datasheet, PDF (1031/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
Figures 21.13 and 21.14 show the operation in interpolated sync plus external sync mode in the
cases of abnormally short and long sectors, respectively.
Intput data
Sync code
detection
Abnormal sector
Sector 1
Sector 3
Sector 4
Sector 5
Sector 6
Maintain
Output data
Sector 1
Sector 3
Sector 4
Sector 5
Abnormal
sector
Figure 21.13 Operation in Interpolated Sync Plus External Sync Mode
(When an Abnormally Short Sector is Encountered)
Intput data
Sector 1
Abnormal sector
Sector 3
Sector 4
Sector 5
Sync code
detection
Maintain
Output data
Sector 1
Sector 3
Abnormal Abnormal
sector
sector
Sector 4
Figure 21.14 Operation in Interpolated Sync Plus External Sync Mode
(When an Abnormally Long Sector is Encountered)
Rev. 2.00 Sep. 07, 2007 Page 999 of 1312
REJ09B0320-0200