SH7261 Datasheet, PDF (17/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

12.3.28 Timer Interrupt Skipping Counter (TITCNT)....................................................... 454
12.3.29 Timer Buffer Transfer Set Register (TBTER) ...................................................... 455
12.3.30 Timer Dead Time Enable Register (TDER).......................................................... 457
12.3.31 Timer Waveform Control Register (TWCR) ........................................................ 458
12.3.32 Bus Master Interface............................................................................................. 459
12.4 Operation ........................................................................................................................... 460
12.4.1 Basic Functions..................................................................................................... 460
12.4.2 Synchronous Operation......................................................................................... 466
12.4.3 Buffer Operation ................................................................................................... 468
12.4.4 Cascaded Operation .............................................................................................. 473
12.4.5 PWM Modes ......................................................................................................... 478
12.4.6 Phase Counting Mode........................................................................................... 483
12.4.7 Reset-Synchronized PWM Mode.......................................................................... 490
12.4.8 Complementary PWM Mode................................................................................ 493
12.4.9 A/D Converter Start Request Delaying Function.................................................. 529
12.4.10 External Pulse Width Measurement...................................................................... 533
12.4.11 Dead Time Compensation..................................................................................... 534
12.4.12 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ....... 536
12.5 Interrupt Sources................................................................................................................ 537
12.5.1 Interrupt Sources and Priorities ............................................................................ 537
12.5.2 DMAC Activation................................................................................................. 539
12.5.3 A/D Converter Activation..................................................................................... 539
12.6 Operation Timing............................................................................................................... 541
12.6.1 Input/Output Timing ............................................................................................. 541
12.6.2 Interrupt Signal Timing......................................................................................... 548
12.7 Usage Notes ....................................................................................................................... 552
12.7.1 Module Standby Mode Setting ............................................................................. 552
12.7.2 Input Clock Restrictions ....................................................................................... 552
12.7.3 Caution on Period Setting ..................................................................................... 553
12.7.4 Contention between TCNT Write and Clear Operations...................................... 554
12.7.5 Contention between TCNT Write and Increment Operations............................... 554
12.7.6 Contention between TGR Write and Compare Match .......................................... 555
12.7.7 Contention between Buffer Register Write and Compare Match ......................... 556
12.7.8 Contention between Buffer Register Write and TCNT Clear ............................... 557
12.7.9 Contention between TGR Read and Input Capture............................................... 558
12.7.10 Contention between TGR Write and Input Capture.............................................. 559
12.7.11 Contention between Buffer Register Write and Input Capture ............................. 560
12.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection .... 560
12.7.13 Counter Value during Complementary PWM Mode Stop .................................... 562
12.7.14 Buffer Operation Setting in Complementary PWM Mode ................................... 562
Rev. 2.00 Sep. 07, 2007 Page xvii of xxxii