SH7261 Datasheet, PDF (508/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(4) Cascaded Operation Example (c)
Figure 12.23 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the
I2AE and I1AE bits in TICCR have been set to 1 to include the TIOC2A and TIOC1A pins in the
TGRA_1 and TGRA_2 input capture conditions, respectively. In this example, the IOA0 to IOA3
bits in both TIOR_1 and TIOR_2 have selected both the rising and falling edges for the input
capture timing. Under these conditions, the ORed result of TIOC1A and TIOC2A input is used for
the TGRA_1 and TGRA_2 input capture conditions.
TCNT_2 value
H'FFFF
H'C256
H'9192
H'6128
H'2064
H'0000
TCNT_1
H'0512
H'0513
H'0514
Time
TIOC1A
TIOC2A
TGRA_1
H'0512
H'0513
H'0514
TGRA_2
H'6128
H'2064
H'C256
Figure 12.23 Cascaded Operation Example (c)
H'9192
Rev. 2.00 Sep. 07, 2007 Page 476 of 1312
REJ09B0320-0200