SH7261 Datasheet, PDF (39/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 1 Overview
Item
Features
Serial communication •
interface with FIFO _•
(SCIF)
•
•
•
I²C bus interface 3
•
(IIC3)
•
Serial sound interface •
(SSI)
•
•
•
•
•
Eight channels
Clock synchronous or asynchronous mode selectable
Simultaneous transmission and reception (full-duplex communication)
supported
Dedicated baud rate generator
Separate 16-byte FIFO registers for transmission and reception
Three channels
Master mode and slave mode supported
Two-channel bidirectional serial transfer
Support of various serial audio formats
Support of master and slave functions
Generation of programmable word clock and bit clock
Multichannel formats
Support of 8, 16, 18, 20, 22, 24 and 32-bit data formats
Controller area
network (RCAN-ET)
[R5S72611]
[R5S72613]
• Two channels
• Supports CAN specification 2.0B
 Data and remote frame in standard format (11-bit ID)
 Data and remote frame in extended format (18-bit ID)
• 16 independent message buffers using IDs in standard (11-bit) or
extended (18-bit) format
• 15 Mailboxes for transmission or reception
• One receive-only Mailbox
• Message reception filtering by IDs:
 Standard message ID
 Extended message ID
• Local reception filter for all Mailboxes (standard and extended IDs) can
be specified
• Power consumption can be reduced in sleep mode
• CAN data transfer rate of up to 1 Mbit/s available
• Transmit message queue having an internal priority sorting
mechanism which handles priority-inversion issue of realtime
applications
• Data buffer access without hand-shaking
Rev. 2.00 Sep. 07, 2007 Page 7 of 1312
REJ09B0320-0200