SH7261 Datasheet, PDF (1190/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 User Debugging Interface (H-UDI)
28.4.2 Reset Types
Table 28.4 Reset Types
ASEMD*
H
RES
L
H
Note: * Fix ASEMD to high.
UDTRST
L
H
L
H
Chip State
Power-on reset and H-UDI reset
Power-on reset
H-UDI reset only
Normal operation
28.4.3 UDTDO Output Timing
The initial value of the UDTDO change timing is to perform data output from the UDTDO pin on
the UDTCK falling edge. However, setting a UDTDO change timing switch command in SDIR
via the H-UDI pin and passing the Update-IR state synchronizes the UDTDO change timing to the
UDTCK rising edge. Hereafter, to synchronize the UDTDO change timing with the UDTCK
falling edge, the UDTRST pin must be asserted simultaneously with a power-on reset or deep
standby mode must be entered. In the case of a power-on reset by the RES pin, the LSI falls in
reset state for a certain period after the RES pin negation. Therefore, when the UDTRST pin is
asserted immediately after the RES pin negation, a UDTDO change timing switch command is
cleared and the UDTDO change timing becomes synchronous with the output of UDTCK falling
edge. To prevent this, at least 20 tcyc must be set between the change timings of the RES pin and
UDTRST pin.
UDTCK
UDTDO
(after execution of
UDTDO change timing
switch command)
UDTDO
(initial value)
t_TDOD
t_TDOD
Figure 28.3 H-UDI Data Transfer Timing
Rev. 2.00 Sep. 07, 2007 Page 1158 of 1312
REJ09B0320-0200