SH7261 Datasheet, PDF (321/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
access. The target address for the dummy read operation does not have to be in the same device as
the target for write access. Furthermore, it does not have to be in the same space.
9.6.3 Note on Transition to Software Standby Mode or Deep Standby Mode
When a transition to software standby mode or deep standby mode is made after write access to
the normal or SDRAM space, there is a possibility that data remains in the internal write buffer of
the BSC. To confirm that no data remain in the write buffer, execute a dummy read of the external
device in the same way as described above.
Rev. 2.00 Sep. 07, 2007 Page 289 of 1312
REJ09B0320-0200