SH7261 Datasheet, PDF (110/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 4 Clock Pulse Generator (CPG)
Figure 4.1 shows a block diagram of the clock pulse generator.
CKIO
XTAL
EXTAL
Crystal
oscillator
On-chip oscillator
PLL circuit 1
(×1, 2, 3, 4, 6, 8)
PLL circuit 2
(×2, 4)
Divider
×1
×1/2
×1/3
×1/4
×1/6
×1/8
×1/12
Internal clock
(Iφ, Max. :
120 MHz (Regular specifications),
100 MHz (Wide-range specifications))
Bus clock
(Bφ = CKIO, Max. 60 MHz)
Peripheral clock
(Pφ, Max. 40 MHz)
MD_CLK1
MD_CLK0
CPG control unit
Clock frequency
control circuit
Standby control circuit
FRQCR
STBCR STBCR2 STBCR3 STBCR4 STBCR5
Bus interface
[Legend]
FRQCR: Frequency control register
STBCR: Standby control register
STBCR2: Standby control register 2
STBCR3: Standby control register 3
STBCR4: Standby control register 4
STBCR5: Standby control register 5
Peripheral bus
Figure 4.1 Block Diagram of Clock Pulse Generator
Rev. 2.00 Sep. 07, 2007 Page 78 of 1312
REJ09B0320-0200