SH7261 Datasheet, PDF (381/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
Table 11.5 List of DMA Transfer Conditions
DMA Transfer
Condition Select
Bits (DSEL)
DSEL = "00"
DSEL = "01"
DSEL = "11"
DMA Transfer Condition
Remarks
Unit operand transfer
• The number of bytes selected for transfer in single
operand transfer (by the OPSEL bits) is transferred
in response to one DMA request.
• Channel arbitration is performed on completion of
each single operand transfer.
Sequential operand transfer
• Transfer in response to a DMA request proceeds in
unit transfer operations until the byte counter
reaches "0".
• Channel arbitration is performed on completion of
each single operand transfer.
Non-stop transfer
• Transfer in response to a DMA request proceeds
continuously until the byte counter reaches "0" by
one DMA request.
OPSEL bit is
disabled
• Once transfer has started, channel arbitration is not
done until it is complete.
Rev. 2.00 Sep. 07, 2007 Page 349 of 1312
REJ09B0320-0200