SH7261 Datasheet, PDF (140/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 5 Exception Handling
5.6 Interrupts
5.6.1 Interrupt Sources
Table 5.8 shows the sources that start up interrupt exception handling. These are divided into
NMI, user breaks, H-UDI, IRQ, PINT, and on-chip peripheral modules.
Table 5.8 Interrupt Sources
Type
NMI
User break
H-UDI
IRQ
PINT
On-chip peripheral module
Request Source
NMI pin (external input)
User break controller (UBC)
User debugging interface (H-UDI)
IRQ0 to IRQ7 pins (external input)
PINT0 to PINT7 pins (external input)
A/D converter (ADC)
CD-ROM decoder (ROM-DEC)
Multifunction timer pulse unit 2 (MTU2)
Realtime clock (RTC)
Watchdog timer (WDT)
I²C bus interface 3 (IIC3)
Direct memory access controller (DMAC)
Serial communication interface with FIFO (SCIF)
Controller area network (RCAN-ET)
IEBus^TM controller (IEB)
Serial sound interface (SSI)
8-bit timer (TMR)
Number of
Sources
1
1
1
8
8
1
6
28
3
1
15
9
32
2
1
2
6
Each interrupt source is allocated a different vector number and vector table offset. See table 6.4
in section 6, Interrupt Controller (INTC), for more information on vector numbers and vector table
address offsets.
Rev. 2.00 Sep. 07, 2007 Page 108 of 1312
REJ09B0320-0200