SH7261 Datasheet, PDF (73/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
Instruction Formats
ni format
15
xxxx nnnn
0
iiii iiii
ni3 format
15
0
xxxx xxxx nnnn x iii
ni20 format
32
16
xxxx nnnn iiii xxxx
Source
Operand
iiiiiiii: Immediate
Destination
Operand
nnnn: Register
direct
nnnn: Register
direct
iii: Immediate
—
iiiiiiiiiiiiiiiiiiii:
Immediate
—
nnnn: Register
direct
iii: Immediate
nnnn: Register
direct
Example
ADD #imm,Rn
BLD #imm3,Rn
BST #imm3,Rn
MOVI20
#imm20, Rn
15
0
iiii iiii iiii iiii
nid format
32
16
xxxx xxxx nnnn xxxx
nnnndddddddddddd —
: Register indirect
with displacement
BLD.B
#imm3,@(disp12,Rn)
15
0
xiii dddd dddd dddd
iii: Immediate
—
nnnndddddddddddd BST.B
: Register indirect #imm3,@(disp12,Rn)
with displacement
iii: Immediate
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
Rev. 2.00 Sep. 07, 2007 Page 41 of 1312
REJ09B0320-0200