SH7261 Datasheet, PDF (716/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.7 Serial Status Register (SCFSR)
SCFSR is a 16-bit register. The upper 8 bits indicate the number of receives errors in the receive
FIFO data register, and the lower 8 bits indicate the status flag indicating SCIF operating state.
The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND,
TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read
(after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. SCFSR is
initialized by a power-on reset or in deep standby mode.
Bit: 15 14 13 12 11 10 9
PER[3:0]
FER[3:0]
Initial value: 0
0
0
0
0
0
0
R/W: R R R R R R R
8
7
6
5
4
3
2
1
0
ER TEND TDFE BRK FER PER RDF DR
0
0
1
1
0
0
R R/(W)*R/(W)*R/(W)*R/(W)* R
0
0
0
R R/(W)*R/(W)*
Note: * Only 0 can be written to clear the flag after 1 is read.
Initial
Bit
Bit Name Value R/W Description
15 to 12 PER[3:0] 0000 R
Number of Parity Errors
Indicate the quantity of data including a parity error in
the receive data stored in the receive FIFO data
register (SCFRDR). After the ER bit in SCFSR is set,
the value indicated by bits 15 to 12 represents the
number of parity errors in SCFRDR. When parity
errors have occurred in all 16-byte receive data in
SCFRDR, PER3 to PER0 show 0.
11 to 8 FER[3:0] 0000 R
Number of Framing Errors
Indicate the quantity of data including a framing error
in the receive data stored in SCFRDR. After the ER
bit in SCFSR is set, the value indicated by bits 11 to 8
represents the number of framing errors in SCFRDR.
When framing errors have occurred in all 16-byte
receive data in SCFRDR, FER3 to FER0 show 0.
Rev. 2.00 Sep. 07, 2007 Page 684 of 1312
REJ09B0320-0200