SH7261 Datasheet, PDF (335/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus Monitor
(3) Bus Timeout Operation in Consecutive Accesses
For transfers where multiple bus accesses are made (such as burst transfer), the next bus access
might not be terminated when a bus timeout occurs. In this case, a bus timeout may occur
continuously.
Even if a bus timeout occurs continuously, the timeout process of terminating a bus access is
performed in the same way as the first time. However, the status is saved in the bus monitor status
register 1 (SYSCESTS1) or bus monitor status register 2 (SYCBESTS2) only the first time.
10.2.4 Combinations of Masters and Bus Errors
The types of detectable bus error depend on the master and access mode.
(1) CPU Transfer Modes and Types of Bus Error Generated
Table 10.6 shows the types of bus error that may be generated by accesses from the CPU.
Table 10.6 CPU Access Types and Types of Bus Error Generated
Access Type
Normal Access
Burst Access
Illegal address access*¹
O*²
O*²*³
Bus timeout*¹
O*²
O*²*³
[Legend]
O: A bus error is generated.
: A bus error is not generated.
Notes: 1. To enable bus error detection, the bus monitor enable register (SYCBEEN) should be
set.
2. To notify the CPU of a bus error, the 00CPEN bit in the bus error control register
(SYCBESW) should be set to 1.
3. The number of bus errors detected is the same as the number of accesses that resulted
in an error.
Rev. 2.00 Sep. 07, 2007 Page 303 of 1312
REJ09B0320-0200