SH7261 Datasheet, PDF (377/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value
R/W Description
31 to 24 DASTS
All 0
R
When read: DMA Arbitration Status
When written: DMA Arbitration Status Clear
These bits are used to verify the status of DMA
transfer on each channel.
• Condition for setting to "1"
• The bit for a channel in which operand transfer
(non-stop transfer) has started is set to "1".
• Condition for clearing to "0"
These bits are cleared to "0" by either of the
following events.
 Correct completion of single operand transfer
(non-stop transfer).
 A "1" is written to the bit.
These bits are not cleared to "0" when DMAC
operation is forcibly ended by the external DMA
transfer forcible end signal. Write "1" to these
bits to clear them.
Note:
In DMA transfer to external devices, the DMA
arbitration status bit (DASTS) can be cleared
before the end of external bus access (once
the last data-write operation has started).
When read:
0: Operand transfer not in progress
1: Operand transfer in progress
When written:
0: Invalid
1: Clears DMA arbitration status
23 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note: Bits 31 to 24 correspond to channels 0 to 7, respectively (31: channel 0, 30: channel
1, …, 24: channel 7)
Rev. 2.00 Sep. 07, 2007 Page 345 of 1312
REJ09B0320-0200