SH7261 Datasheet, PDF (768/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
17.3.2 I²C Bus Control Register 2 (ICCR2)
ICCR2 is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA
pin, monitors the SCL pin, and controls reset in the control part of the I²C bus.
ICCR2 is initialized to H'7D by a power-on reset or deep standby mode.
Bit: 7
6
5
4
3
BBSY SCP SDAO SDAOP SCLO
Initial value: 0
1
1
1
1
R/W: R/W R/W R/W R/W R
2
1
0
— IICRST —
1
0
1
R R/W R
Initial
Bit
Bit Name Value R/W Description
7
BBSY
0
R/W Bus Busy
Enables to confirm whether the I²C bus is occupied or
released and to issue start/stop conditions in master
mode. With the clocked synchronous serial format, this
bit is always read as 0. With the I²C bus format, this bit
is set to 1 when the SDA level changes from high to low
under the condition of SCL = high, assuming that the
start condition has been issued. This bit is cleared to 0
when the SDA level changes from low to high under the
condition of SCL = high, assuming that the stop
condition has been issued. Write 1 to BBSY and 0 to
SCP to issue a start condition. Follow this procedure
when also re-transmitting a start condition. Write 0 in
BBSY and 0 in SCP to issue a stop condition.
6
SCP
1
R/W Start/Stop Issue Condition Disable
Controls the issue of start/stop conditions in master
mode. To issue a start condition, write 1 in BBSY and 0
in SCP. A retransmit start condition is issued in the
same way. To issue a stop condition, write 0 in BBSY
and 0 in SCP. This bit is always read as 1. Even if 1 is
written to this bit, the data will not be stored.
Rev. 2.00 Sep. 07, 2007 Page 736 of 1312
REJ09B0320-0200