SH7261 Datasheet, PDF (1169/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Power-Down Modes
27.2.7 System Control Register 2 (SYSCR2)
SYSCR2 is an 8-bit readable/writable register that enables or disables write to the on-chip RAM.
SYSCR2 is initialized to H'FF by a power-on reset or in deep standby mode but retains its
previous value by a manual reset or in software standby mode. Only byte access is valid.
When an RAMWE bit is set to 1, the corresponding on-chip RAM area is enabled. When an
RAMWE bit is cleared to 0, the corresponding on-chip RAM area cannot be written to. In this
case, writing to the on-chip RAM is ignored. The initial value of an RAMWE bit is 1.
Note that when clearing the RAMWE bit to 0 to disable the on-chip RAM, be sure to execute an
instruction to read from or write to the same arbitrary address in each page before setting the
RAMWE bit. If such an instruction is not executed, the data last written to each page may not be
written to the on-chip RAM. Furthermore, an instruction to access the on-chip RAM should not be
placed immediately after the instruction to write to SYSCR2. If an on-chip RAM access
instruction is set, normal access is not guaranteed.
Note: When writing to this register, see section 27.4, Usage Note.
Bit: 7
6
5
4
3
2
1
0






RAM RAM
WE1 WE0
Initial value: 1
1
1
1
1
1
1
1
R/W: R R R R R R R/W R/W
Bit
7 to 2
1
0
Initial
Bit Name Value R/W Description

All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
RAMWE1 1
R/W RAM Write Enable 1 (corresponding RAM addresses:
H'FFF84000 to H'FFF87FFF)
0: On-chip RAM write disabled
1: On-chip RAM write enabled
RAMWE0 1
R/W RAM Write Enable 0 (corresponding RAM addresses:
H'FFF80000 to H'FFF83FFF)
0: On-chip RAM write disabled
1: On-chip RAM write enabled
Rev. 2.00 Sep. 07, 2007 Page 1137 of 1312
REJ09B0320-0200